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general description the max3815 cable equalizer automatically provides compensation for dvi, hdmi, dfp, panellink , and adc cables. it extends the usable cable distance up to 36 meters. the max3815 is designed to equalize sig- nals encoded in the transition-minimized differential signaling (tmds ) format. the max3815 features four cml-differential inputs and outputs (three data and one clock). it provides a loss- of-signal (los) output that indicates loss-of-clock sig- nal. the outputs include a disable function or the equalizer can be powered down to conserve power. for direct chip-to-chip communication, the output dri- vers can be switched to one-half the dvi output specifi- cation to conserve power and reduce emi. equalization can be automatic or set to manual control for specific in-cable applications. the max3815 is available in a 7mm x 7mm, 48-pin tqfp-ep package and operates over a 0? to +70? temperature range. applications front-projector dvi/hdmi inputs high-definition televisions and displays dvi-d/hdmi cable-extender modules and active cable assemblies lcd computer monitors features ? extends tmds cable reach to projectors or monitors using dvi, dfp, panellink, adc, or hdmi interfaces ? extends tmds interface length as follows: 0 to 50 meters over dvi-cable, 24 awg stp (shielded-twisted pair) 0 to 36 meters over dvi-cable, 28 awg stp 0 to 30 meters over dvi-cable, 30 awg stp ? compatible with dtv resolutions 480i, 480p, 720p, 1080i, and 1080p ? compatible with computer resolutions vga, svga, xga, sxga, uxga ? fully automatic equalization up to 40db at 825mhz (1.65gbps), no system control required ? 3.3v power supply ? power dissipation of 0.6w (typ) ? 7mm x 7mm 48-pin tqfp lead-free package max3815 tmds digital video equalizer for dvi/hdmi cables ________________________________________________________________ maxim integrated products 1 ordering information rgb/hv adc/sync tmds deserializer select image scaler and processor panel interface timing and drivers lcd, dlp, or lcos vga input dvi-d input dvi-d cable up to 36m or 120ft (28awg stp) laptop video projector max3815 equalizer typical application circuits 19-3466; rev 2; 2/08 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. evaluation kit available part temp range pin- package pkg code MAX3815CCM 0? to +70? 48 tqfp-ep* c48e-8 MAX3815CCM+ 0? to +70? 48 tqfp-ep* c48e-8 + denotes lead-free package. *ep = exposed pad. typical application circuits continued at end of data sheet. pin configuration appears at end of data sheet. dvi is a trademark of digital display working group. hdmi is a trademark of hdmi licensing, llc. panellink and tmds are registered trademarks of silicon image, inc.
max3815 tmds digital video equalizer for dvi/hdmi cables 2 _______________________________________________________________________________________ absolute maximum ratings stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. supply voltage v cc ..............................................-0.5v to +4.0v voltage at all i/o pins.................................-0.5v to (v cc + 0.7v) voltage between any cml i/o complementary pair ..........?.3v continuous power dissipation (t a = +70 c) 48-pin tqfp-ep (derate 36.2mw/ c above +70 c) ..2896mw operating junction temperature range ...........-55? to +150? storage temperature range .............................-55? to +150? die attach temperature...................................................+400? electrical characteristics (v cc = +3.0v to +3.6v, t a = 0? to +70?. typical values are at v cc = +3.3v, external terminations = 50 ?%, tmds rate = 250mbps to 1.65gbps, t a = +25?, unless otherwise noted.) parameter symbol conditions min typ max units pwrdwn = high 165 230 power-supply current i cc pwrdwn = low 10 ma supply-noise tolerance dc to 500khz 200 mv p-p equalizer performance 1db skin-effect loss at 825mhz 0.2 24db skin-effect loss at 825mhz 0.2 residual output jitter (cables only) 0.25gbps to 1.65gbps (notes 1, 2, and 3) 40db skin-effect loss at 825mhz 0.2 ui cid tolerance 20 bits control and status clklos assert level differential peak-to-peak at eq input with 165mhz clock 50 mv p-p cml inputs (cable side) differential input voltage swing v id at cable input 800 1000 1400 mv p-p common-mode input voltage v cm v cc - 0.4 v cc + 0.1 v input resistance r in single-ended 45 50 55 cml outputs (asic side) outlevel = high 800 1000 1200 differential output-voltage swing v od 50 load, each side to v cc outlevel = low 350 500 650 mv p-p output-voltage high single-ended, outlevel = high v cc mv output-voltage low single-ended, outlevel = high v cc - 600 v cc - 400 mv output voltage during power-down single-ended, pwrdwn = low v cc - 10 v cc +10 mv
max3815 tmds digital video equalizer for dvi/hdmi cables _______________________________________________________________________________________ 3 electrical characteristics (continued) (v cc = +3.0v to +3.6v, t a = 0? to +70?. typical values are at v cc = +3.3v, external terminations = 50 ?%, tmds rate = 250mbps to 1.65gbps, t a = +25?, unless otherwise noted.) parameter symbol conditions min typ max units common-mode output voltage 50 load, each side to v cc , outlevel = high v cc - 0.25 v rise/fall time (note 1) 20% to 80% 80 130 200 ps lvttl control and status interface lvttl input high voltage v ih 2.0 v lvttl input low voltage v il 0.8 v lvttl input high current v ih(min) < v in < v cc -50 ? lvttl input low current gnd < v in < v il(max) -100 ? open-collector output high r load 10k to v cc 2.4 v open-collector output low r load 2k to v cc 0.4 v open-collector output sink 5ma note 1: ac specifications are guaranteed by design and characterization. note 2: cable input swing is 800mv to 1400mv differential peak-to-peak. residual output jitter is defined as peak-to-peak determin- istic jitter + 14.2 times random jitter. note 3: test pattern is a 2 7 - 1 prbs + 20 ones + 2 7 - 1 prbs (inverted) + 20 zeros. typical operating characteristics (typical values are at v cc = +3.3v, t a = +25?, data pattern = 2 7 - 1 prbs + 20 ones + 2 7 - 1 prbs (inverted) + 20 zeros, unless otherwise noted.) supply current vs. temperature max3815 toc01 temperature ( c) supply current (ma) 60 50 30 40 20 10 110 120 130 140 150 160 170 180 190 200 100 070 outlevel = high outlevel = low differential input return loss vs. frequency max3815 toc02 frequency (mhz) gain (db) 2500 2000 1500 1000 500 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 -50 0 3000 equalizer input after 205ft of gore 89 cable (top) equalizer output (bottom) max3815 toc03 5ns/div 128mv/div 350mv/div data rate = 1.65gbps 40db cable skin-effect loss at 825mhz
max3815 tmds digital video equalizer for dvi/hdmi cables 4 _______________________________________________________________________________________ typical operating characteristics (continued) (typical values are at v cc = +3.3v, t a = +25?, data pattern = 2 7 - 1 prbs + 20 ones + 2 7 - 1 prbs (inverted) + 20 zeros, unless otherwise noted.) equalizer input eye after 205ft of gore 89 cable (top) equalizer output (bottom) max3815 toc04 152ps/div 350mv/div data rate = 1.65gbps 40db cable skin-effect loss at 825mhz equalizer input eye after 205ft of gore 89 cable (top) equalizer output (bottom) max3815 toc05 1ns/div 300mv/div data rate = 250mbps 40db cable skin-effect loss at 825mhz equalizer eyes after 100ft madison digital flat-panel cable, 28 awg (data rate = 1.65gbps) max3815 toc06 200ps/div 350mv/div equalizer eyes after 100ft madison digital flat-panel cable, 28 awg (data rate = 350mbps) max3815 toc07 1ns/div 350mv/div equalizer eyes after 3ft cable (data rate = 1.65gbps) max3815 toc08 200ps/div 350mv/div jitter vs. data rate after 205ft cable with 40db skin-effect loss at 825mhz max3815 toc09 data rate (mbps) jitter (ps p-p ) 1450 1250 450 650 850 1050 20 40 60 80 100 120 0 250 1650 gore 89 cable residual jitter = dj + 14.2 x rj deterministic jitter total jitter vs. power-supply noise frequency (data rate = 1.65gbps) max3815 toc10 frequency (khz) total jitter (ps p-p ) 10,000 1000 10 100 110 120 130 140 150 160 170 180 100 1 100,000 noise amplitude: 200mv p-p data through 100ft madison digital flat-panel cable, 28awg 0 0.2 0.1 0.4 0.3 0.5 0.6 0 100 50 150 200 deterministic jitter vs. cable length (tensolite twin-ax 28 awg) max3815 toc11 cable length (ft) deterministic jitter (ui p-p ) 1.65gbps 800mbps 250mbps no eq with max3815 eq residual jitter vs. signal amplitude input to cable (data rate = 1.65gbps) max3815 toc12 differential amplitude (mv p-p ) residual jitter (ps p-p ) 1.2 1.0 0.8 70 80 90 100 110 120 60 0.6 1.4 205ft of gore 89 cable with 40db skin- effect loss at 825mhz residual jitter = dj + 14.2 x rj
max3815 tmds digital video equalizer for dvi/hdmi cables _______________________________________________________________________________________ 5 -1.0 -0.7 -0.8 -0.9 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0 040 20 60 80 100 120 eqcontrol voltage (relative to v cc ) vs. cable length (manual eq control) max3815 toc13 cable length (ft) eqcontrol voltage (v) cable is tensolite twin-ax 28 awg with approximately 0.34db of loss per foot at 825mhz residual jitter at 1.65gbps eqcontrol voltage 0 60 40 20 80 100 120 140 160 180 200 residual jitter (ps p-p ) equalizer output eye after 120ft of cable (data rate = 1.65gbps) max3815 toc14 cable is tensolite twin-ax 28 awg 200mv/div 100ps/div 0 100 50 200 150 300 250 350 04060 20 80 100 120 loss-of-clock assert threshold vs. cable length max3815 toc15 cable length (ft) differential clock amplitude (mv p-p ) 165mhz clock frequency 25mhz clock frequency cable is tensolite twin-ax 28 awg typical operating characteristics (continued) (typical values are at v cc = +3.3v, t a = +25?, data pattern = 2 7 - 1 prbs + 20 ones + 2 7 - 1 prbs (inverted) + 20 zeros, unless otherwise noted.) pin description pin name function 1, 4, 5, 8, 9, 12, 13, 16, 38, 41, 43, 44 v cc supply voltage. all pins must be connected to v cc . 2 rx0_in- negative data input, cml 3 rx0_in+ positive data input, cml 6 rx1_in- negative data input, cml 7 rx1_in+ positive data input, cml 10 rx2_in- negative data input, cml 11 rx2_in+ positive data input, cml 14 rxc_in+ positive clock input, cml 15 rxc_in- negative clock input, cml 17 eqcontrol equalizer control. this pin allows the user to control the equalization level of the max3815. connect the pin to gnd for automatic operation. set the voltage to v cc / 2 for minimum equalization, or set the voltage between v cc - 1v to v cc for manual equalization. see the typical operating characteristics for more information. 18 clklos loss-of-clock signal output, lvttl open collector. this pin asserts low upon loss of the input tmds clock from the cable. 19 pwrdwn power-down input, lvttl. this input allows the ic to be powered down to conserve power. connect high for normal operation. pull low for power-down mode.
max3815 detailed description the max3815 tmds equalizer accepts differential cml input data at rates of 250mbps up to 1.65gbps (individ- ual channel data rate). it automatically adjusts to atten- uation levels of up to 40db at 825mhz due to skin-effect losses in copper cable. it consists of four cml input buffers, a loss-of-clock signal detector, three independent adaptive equalizers, four limiting ampli- fiers, and four output buffers (figure 1). cml input buffers and output drivers the input buffers and the output drivers are implement- ed using current-mode logic (cml) (see figures 3 and 4). the output drivers are open-collector and can be turned off with the outon pin, or can be set to output a one-half amplitude signal (500mv p-p differential) using the outlevel pin. for details on interfacing with cml, refer to maxim application note hfan-01.0: introduction to lvds, pecl, and cml . loss-of-clock signal detector the loss-of-clock signal detector indicates a loss-of- clock signal at the clklos pin. adaptive equalizer the three data channels each contain an independent adaptive equalizer. each channel analyzes the incom- ing signal and determines the amount of equalization to apply. limiting amplifier the limiting amplifier amplifies the signal from the adaptive equalizer and truncates the top and bottom of the waveform to provide a clean high- and low-level signal to the output drivers. applications information typical shielded twisted pair (stp) and unshielded twisted pair (utp) cables exhibit skin-effect losses, which attenuate the high-frequency spectrum of a tmds signal, eventually causing data errors or even closing the signal eye altogether given a long enough cable. the max3815 recovers the data and opens the signal eye through compensating equalization. the basic tmds interface is composed of four differen- tial serial links: three links carry serial data up to 1.65gbps each, and the fourth is a one-tenth-rate (0.1x) clock that operates up to 165mhz. tmds, as with tmds digital video equalizer for dvi/hdmi cables 6 _______________________________________________________________________________________ pin description (continued) pin name function 20, 23, 24, 25, 28, 29, 32, 33, 36, 37, 42 gnd ground 21 rxc_out- negative clock output, cml 22 rxc_out+ positive clock output, cml 26 rx2_out+ positive data output, cml 27 rx2_out- negative data output, cml 30 rx1_out+ positive data output, cml 31 rx1_out- negative data output, cml 34 rx0_out+ positive data output, cml 35 rx0_out- negative data output, cml 39 outlevel output-level control input, lvttl. this input sets the output amplitude to the standard dvi level (1000mv p-p ) when high, and sets the output amplitude to 1/2 the dvi level (500mv p-p ) when low. 40 outon output-enable control input, lvttl. this input enables the cml outputs when forced low and sets a differential logic zero when forced high. 45?8 n.c. no connection ep exposed pad ground. the exposed pad must be soldered to the circuit-board ground for proper thermal and electrical operation.
analog nvga links, must handle a variety of resolutions and screen update rates. the actual range of digital serial rates is roughly 250mbps to 1.65gbps. for appli- cations requiring ultra-high resolutions (e.g., qxga), a ?ouble-link?tmds interface is used and is composed of six data links plus the clock, requiring two max3815 ics with the clock going to both ics. see figure 2. the max3815 can be used to extend any tmds inter- face as used under the following trademarked names: dvi (digital visual interface), dfp (digital flat-panel), panellink, adc (apple display connector), and hdmi (high-definition multimedia interface). loss-of-clock signal ( clklos ) output loss-of-clock signal is indicated by the clklos out- put. a low level on clklos indicates that the signal power on the rxc_in pins has dropped below a threshold. when there is sufficient input voltage to the channel (typically greater than 100mv p-p differential), clklos is high. the clklos output is suitable for indicating problems with the transmission link caused by, for example, a broken cable, a defective driver, or a lost connection to the equalizer. max3815 tmds digital video equalizer for dvi/hdmi cables _______________________________________________________________________________________ 7 input buffer driver adaptive eq limiting amplifier terminated 3.3v cml input buffer driver adaptive eq limiting amplifier terminated 3.3v cml input buffer driver adaptive eq limiting amplifier terminated 3.3v cml input buffer driver limiting amplifier terminated 3.3v cml rxc_out+/- outlevel rx0_out+/- rx1_out+/- rx2_out+/- rx2_in+/- rx1_in+/- rx0_in+/- rxc_in+/- clklos eqcontrol outon clock los detector max3815 figure 1. functional diagram max3815 max3815 d0 d1 d2 d3 d4 d5 d0 d1 d2 d3 d4 d5 clk clk figure 2. connection scheme for max3815 in dual link application adc is a trademark of apple computer, inc. dfp is a trademark of video electronics standards association (vesa).
max3815 a squelching function can be created by sending the clklos output through an inverter to the outon pin. this will squelch the cml outputs whenever the clock signal is removed. a loss-of-signal led indicator can be incorporated into the circuit as well (see figure 3). output level control (outlevel) input the outlevel pin is an lvttl input that allows the user to select between standard output amplitude (1000mv p-p differential) or one-half output amplitude (500mv p-p differential). forcing this pin high results in the standard output signal level, and forcing this pin low results in the reduced output signal level. equalizer control (eqcontrol) input the eqcontrol pin allows the user to control the equalization in one of three ways: forcing the pin to ground sets the equalizer in automatic equalization mode, forcing the pin to v cc / 2 sets the equalizer to minimum equalization, and forcing a voltage between v cc - 1v to v cc allows manual control of the equaliza- tion level applied to the input signals. see the typical operating characteristics for more information. power-down ( pwrdwn ) input the pwrdwn pin allows the part to be powered down to reduce system power consumption. force the pin high for normal operation. force the pin low to power- down the ic. when powered down, the part consumes approximately 10ma. output on ( outon ) input the outon pin is an lvttl input. force the pin low to enable the outputs. force the pin high to set a differential zero on the outputs. when disabled, the outputs will go to a differential zero, irrespective of the signal at the inputs. cable selection tmds performance is heavily dependent on cable quality. deterministic jitter (dj) can be caused by dif- ferential-to-common-mode conversion (or vice-versa) tmds digital video equalizer for dvi/hdmi cables 8 _______________________________________________________________________________________ max3815 v cc rx_in+/- 50 figure 4. simplified input circuit schematic max3815 rx_out+ rx_out- v cc figure 5. simplified output circuit schematic interface models 10k 4.7k v cc outon 200 loss-of-clock led clklos figure 3. squelch circuit
within a twisted pair (stp or utp), usually a result of cable twist or dielectric imbalance. refer to application note hfan-04.5.4: ?itter happens?when a twisted pair is unbalanced for more information. layout considerations the data and clock inputs are the most critical paths for the max3815 and great care should be taken to mini- mize discontinuities on these transmission lines between the connector and the ic. here are some sug- gestions for maximizing the performance of the max3815: the data and clock inputs should be wired directly between the cable connector and ic without stubs. input and output data channel designations are only a guide. polarity assignments can be swapped and channel paths can be interchanged. an uninterrupted ground plane should be posi- tioned beneath the high-speed i/os. ground-path vias should be placed close to the ic and the input/output interfaces to allow a return cur- rent path to the ic and the dvi cable. maintain 100 differential transmission line imped- ance into and out of the max3815. use good high-frequency layout techniques and multilayer boards with an uninterrupted ground plane to minimize emi and crosstalk. exposed-pad package the exposed pad on the 48-pin tqfp-ep provides a very low thermal resistance path for heat removal from the ic. the pad is also electrical ground on the max3815 and must be soldered to the circuit board ground for proper thermal and electrical performance. refer to maxim application note hfan-08.1: thermal considerations of qfn and other exposed-paddle packages for additional information. chip information process: sige bipolar max3815 tmds digital video equalizer for dvi/hdmi cables _______________________________________________________________________________________ 9 5 20 10 40 30 50 60 32 awg 28 awg 30 awg 26 awg 24 awg 22 awg typical max3815 cable reach dvi wire gauge cable length (meters) limit of cable length without eq at 1.65gbps typical dvi wire gauge range shaded area = max3815 usable cable length range at all dvi rates up to 1.65gbps figure 6. cable reach package information (for the latest package outline information, go to www.maxim-ic.com/packages .) package type document no. 48 tqfp 21-0065
max3815 tmds digital video equalizer for dvi/hdmi cables 10 ______________________________________________________________________________________ max3815 equalizer max3816 ddc extender hdtv up to 36m of dvi-d or hdmi cable (28 awg) standard length dvi-d or hdmi cable digital broadcast digital cable digital satellite dvd blu-ray disc dvi-d or hdmi extender box video source blu-ray disc is a trademark of blu-ray disc association. typical application circuits (continued) max3815 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 v cc rx0_in- rx0_in+ v cc v cc rx1_in- rx1_in+ v cc v cc rx2_in- rx2_in+ v cc n.c. n.c. n.c. n.c. v cc v cc gnd v cc outlevel v cc gnd gnd rx0_out- rx0_out+ gnd gnd rx1_out- rx1_out+ gnd gnd rx2_out- rx2_out+ gnd v cc rxc_in+ rxc_in- v cc eqcontrol gnd rxc_out- rxc_out+ gnd gnd clklos pwrdwn outon top view 48 tqfp-ep pin configuration
max3815 tmds digital video equalizer for dvi/hdmi cables maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 11 2008 maxim integrated products is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 0 10/04 initial release. 1 8/05 removed future status from the lead-free package in the ordering information table. 1 2 2/08 removed reference to the s chematic and board layers in the layout considerations section. 9

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